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february 2012 doc id 018746 rev 2 1/1 1 stm32f051x4 stm32f051x6 stm32f051x8 low- and medium-density advanc ed arm?-based 32-bit mcu with 16 to 64 kbytes flash, timers , adc, dac and comm. interfaces features operating conditions: ? voltage range: 2.0 v to 3.6 v arm 32-bit cortex?-m0 cpu (48 mhz max) memories ? 16 to 64 kbytes of flash memory ? 8 kbytes of sram with hw parity checking crc calculation unit clock management ? 4 to 32 mhz crystal oscillator ? 32 khz oscillator for rtc with calibration ? internal 8 mhz rc with x6 pll option ? internal 40 khz rc oscillator calendar rtc with alarm and periodic wakeup from stop/standby reset and supply management ? power-on/power down reset (por/pdr) ? programmable voltage detector (pvd) low power sleep, stop, and standby modes v bat supply for rtc and backup registers 5-channel dma controller 1 12-bit, 1.0 s adc (up to 16 channels) ? conversion range: 0 to 3.6v ? separate analog supply from 2.4 up to 3.6 two fast low-power analog comparators with programmable input and output one 12-bit d/a converter up to 55 fast i/os ? all mappable on external interrupt vectors ? up to 36 i/os with 5 v tolerant capability up to 18 capacitive sensing channels supporting touchkey, li near and rotary touch sensors 96-bit unique id serial wire debug (swd) up to 11 timers ? one 16-bit 7-channel advanced-control timer for 6 channels pwm output, with deadtime generation and emergency stop ? one 32-bit and one 16-bit timer, with up to 4 ic/oc, usable for ir control decoding ? one 16-bit timer, with 2 ic/oc, 1 ocn, deadtime generation and emergency stop ? two 16-bit timers, each with ic/oc and ocn, deadtime generation, emergency stop and modulator gate for ir control ? one 16-bit timer with 1 ic/oc ? independent and system watchdog timers ? systick timer: 24-bit downcounter ? one 16-bit basic timer to drive the dac communication interfaces ? up to two i 2 c interfaces; one supporting fast mode plus (1 mbit/s) with 20 ma current sink, smbus/pmbus, and wakeup from stop ? up to two usarts supporting master synchronous spi and modem control; one with iso7816 interface, lin, irda capability, auto baud rate detection and wakeup feature ? up to two spis (18 mbit/s) with 4 to 16 programmable bit frame, 1 with i 2 s interface multiplexed ? hdmi cec interface, wakeup on header reception table 1. device summary reference part number stm32f051x4 stm32f051k4, stm32f051c4, stm32f051r4 stm32f051x6 stm32f051k6, stm32f051c6, stm32f051r6 stm32f051x8 stm32f051c8, stm32f051r8, stm32f051k8 lqfp64 10x10 lqfp48 7x7 ufqfpn32 5x5 www.st.com
contents stm32f051x 2/3 doc id 018746 rev 2 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 arm? cortextm-m0 core with embedded flash and sram . . . . . . . . . 10 3.2 memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.3 cyclic redundancy check calculation unit (crc) . . . . . . . . . . . . . . . . . . . 10 3.4 direct memory access controller (dma) . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.5 nested vectored interrupt controller (nvic) . . . . . . . . . . . . . . . . . . . . . . . 11 3.6 extended interrupt/event controller (exti) . . . . . . . . . . . . . . . . . . . . . . . . 11 3.7 clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.8 boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.9 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.9.1 power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.9.2 power supply supervisors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.9.3 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.10 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.11 real-time clock (rtc) and backup registers . . . . . . . . . . . . . . . . . . . . . . 14 3.12 timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.12.1 advanced-control timer (tim1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.12.2 general-purpose timers (tim2..3, tim14..17) . . . . . . . . . . . . . . . . . . . . 16 3.12.3 basic timer tim6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.12.4 independent window watchdog (iwwdg) . . . . . . . . . . . . . . . . . . . . . . . 17 3.12.5 system window watchdog (wwdg) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.12.6 systick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.13 inter-integrated circuit interfaces (i 2 c) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.14 universal synchronous/asynchronous receiver transmitters (usart) . . . 18 3.15 serial peripheral interface (spi)/inter-integrated sound interfaces (i 2 s) . 19 3.16 high-definition multimedia interface (hdmi) - consumer electronics control (cec) 20 3.17 general-purpose inputs/outputs (gpios) . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.18 touch sensing controller (tsc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
stm32f051x contents doc id 018746 rev 2 3/3 3.19 analog to digital converter (adc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.19.1 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.19.2 v bat battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.20 digital-to-analog converter (dac) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.21 fast low power comparators and reference voltage . . . . . . . . . . . . . . . . . 22 3.21.1 serial wire debug port (sw-dp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4 pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7 ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
list of tables stm32f051x 4/4 doc id 018746 rev 2 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. stm32f051xx family device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 4. comparison of i2c analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 5. stm32f051xx i 2 c implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 6. stm32f051xx usart implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 7. stm32f051x spi/i2s implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 8. capacitive sensing gpios available on stm32f051x devices . . . . . . . . . . . . . . . . . . . . . 20 table 9. no. of capacitive sensing channels available on stm32f051xx devices. . . . . . . . . . . . . . 21 table 10. legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 11. pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 12. alternate functions selected through gpioa_afr registers for port a . . . . . . . . . . . . . . . 29 table 13. alternate functions selected through gpiob_afr registers for port b . . . . . . . . . . . . . . . 30 table 14. stm32f051x peripheral register boundary addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 15. lqfp64 ? 10 x 10 mm 64 pin low-profile quad flat package mechanical data . . . . . . . . . . 35 table 16. lqfp48 ? 7 x 7mm, 48-pin low-profile quad flat package mechanical data. . . . . . . . . . . . 36 table 17. ufqfpn32 - 32-lead ultra thin fine pitch quad flat no-lead package (5 x 5), package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 18. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
stm32f051x list of figures doc id 018746 rev 2 5/5 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 2. clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 3. lqfp64 64-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 4. lqfp48 48-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 5. ufqfpn32 32-pin package pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 6. stm32f051x memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 7. lqfp64 ? 10 x 10 mm 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . 35 figure 8. recommended footprint (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 9. lqfp48 ? 7 x 7mm, 48-pin low-profile quad flat package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 10. recommended footprint (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 11. ufqfpn32 - 32-lead ultra thin fine pitch quad flat no-lead package outline (5 x 5). . . . . . 37 figure 12. ufqfpn32 recommended footprint (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
description stm32f051x 6/9 doc id 018746 rev 2 1 description the stm32f051xx family incorporates the high-performance arm cortex?-m0 32-bit risc core operating at a 48 mhz frequency, high-speed embedded memories (flash memory up to 64 kbytes and sram up to 8 kbytes), and an extensive range of enhanced peripherals and i/os. all devices offer standard communication interfaces (up to two i 2 cs, two spis, one i2s, one hdmi cec, and up to two usarts), one 12-bit adc, one 12-bit dac, up to five general-purpose 16-bit timers, a 32-bit timer and an advanced-control pwm timer. the stm32f051xx family operates in the -40 to +85 c and -40 to +105 c temperature ranges, from a 2.0 to 3.6 v power supply. a comprehensive set of power-saving modes allows the design of low-power applications. the stm32f051xx family includes devices in th ree different packages ranging from 32 pins to 64 pins. depending on the device chosen, di fferent sets of peripherals are included. the description below provides an overview of the complete range of peripherals proposed in this family. these features make the stm32f051xx microcontroller family suitable for a wide range of applications such as application control and user interfaces, handheld equipment, a/v receivers and digital tv, pc peripherals, gaming and gps platforms, industrial applications, plcs, inverters, printers, scanners, alarm systems, video intercoms, and hvacs.
stm32f051x description doc id 018746 rev 2 7/9 table 2. stm32f051xx family device features and peripheral counts peripheral stm32f051kx stm32f051cx stm32f051rx flash (kbytes) 16 32 64 16 32 64 16 32 64 sram (kbytes) 484848 timers advanced control 1 (16-bit) general purpose 5 (16-bit) 1 (32-bit) basic 1 (16-bit) comm. interfaces spi (i2s) (1) 1(1) (2) 2(1) 1(1) (2) 2(1) 1(1) (2) 2(1) i 2 c1 (3) 21 (3) 21 (3) 2 usart 1 (4) 21 (4) 21 (4) 2 cec 1 12-bit synchronized adc (number of channels) 1 (10 ext. + 3 int.) 1 (16 ext. + 3 int.) gpios 273955 capacitive sensing channels 14 17 18 12-bit dac (number of channels) 1 (1) analog comparator 2 max. cpu frequency 48 mhz operating voltage 2.0 to 3.6 v operating temperature ambient operating temperature: -40 c to 85 c / -40 c to 105 c junction temperature: -40 c to 125 c packages ufqfpn32 lqfp48 lqfp64 1. the spi1 interface can be used either in spi mode or in i2s audio mode. 2. spi2 is not present 3. i2c2 is not present 4. usart2 is not present
device overview stm32f051x 8/9 doc id 018746 rev 2 2 device overview figure 1. block diagram 0!; = %84)4 .6)# bit!$# !$inputs 37#,+ 37$!4 .234 6 $$ to 6 6 !& !(" 32!- 7+50 6 33 3#,3$! )# 6 $$! '0$-! channels 84!, /3# -(z 84!, k(z /3#). 0& /3#/54 0& /3#?/54 /3#?). !("0#,+ (#,+ !0"0#,+ as !& &,!3( 6/,4 2%' 64 / 6 6 $$ 0/7%2 24# interface as!& "us-atrix bits )nterface +" 24# #/24%8 -#05 f (#,+ -(z obl flash 30) "ackup reg 3#,3$!3-"al )# as !& 4emp sensor 6 33! channels compl channels "2+ %42 input as !& ch%42as!& &#,+ 0ower )77$' 6 $$ 637 0/2 0$2 3500,9 6 $$! 6 $$! 6 $$! 6 "!4 6 to 6 2848 #43 243 #+ as !& 2848 #43 243 #+ as !& .6)# 30))3 )& #ontroller 6 $$! 350%26)3)/. 06$ 2eset )nt 6 $$ !0" 0/2 4!-0%2 24# 2%3%4 #,/#+ #/.42/, !$##,+ 0,, bit$!# )& )& )& 6 $$! $!#?/54 as !& 4)-%2 !,!2- /54 3erial7ire $ebug #%##,+ -)3/-#+ 0";= 0#;= 0$ 0&; = channels ch%42as!& channelas!& 6 $$ +" ($-) #%# #%# as !& 2#(3-(z 53!24#,+ channel compl"2+as!& channel compl"2+as!& compl "2+ as !& controller 32!- #2# 4ouch 3ensing #ontroller '0 #om parat or '0 #omparator ).054 /54054 393#&' )& groupsof channels !nalog switches 6 $$! m! for &- )2?/54as!& $"'-#5 !(" decoder 39.# -36 4)-%2 4)-%2 4)-%2 4)-%2 4)-%2 4)-%2 4)-%2 53!24 53!24 '0)/port! '0)/port" '0)/port# '0)/port$ '0)/port& -/3) -)3/ 3#+ .33 as !& 2#(3-(z 2#,3 3#+#+ ).054 as!& -/3)3$ .3373as!& 77$'
stm32f051x device overview doc id 018746 rev 2 9/9 figure 2. clock tree -(z (3%/3# /3#?). /3#?/54 /3#?). /3#?/54 -(z (3)2# to)77$' 0,, xx x 0,,-5, -#/ -ainclock output !(" 0,,#,+ (3) (3% !0" prescaler !$# 0rescaler (#,+ 0,,#,+ to!("buscore memoryand$-! to!$# -(zmax ,3% ,3) (3) (3) (3% to24# 0,,32# 37 -#/ 393#,+ 24##,+ 24#3%,;= )77$'#,+ 393#,+ to4)- )f!0"prescaler xelsex &,)4&#,+ to&lashprogramminginterface (3) -(z (3)2# (3) ,3% to)# to53!24 ,3% (3) 393#,+ 0#,+ 393#,+ (3) 0#,+ -36 to)3 to#%# tocortex3ystemtimer &(#,+#ortexfreerunningclock to!0"peripherals !(" prescaler #33 ,3%/3# k(z ,3)2# k(z
functional overview stm32f051x 10/22 doc id 018746 rev 2 3 functional overview 3.1 arm ? cortex tm -m0 core with embedded flash and sram the arm cortex?-m0 processor is the latest generation of arm processors for embedded systems. it has been developed to provide a low-cost platform that meets the needs of mcu implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts. the arm cortex?-m0 32-bit risc processor features exceptional code-efficiency, delivering the high-performance expected from an arm core in the memory size usually associated with 8- and 16-bit devices. the stm32f051xx family has an embedded arm core and is therefore compatible with all arm tools and software. figure 1 shows the general block diagram of the device family. 3.2 memories the device has the following features: up to 8 kbytes of embedded sram accessed (read/write) at cpu clock speed with 0 wait states and featuring embedded parity checking with exception generation for fail- critical applications. the non-volatile memory is divided into two arrays: ? 16 to 64 kbytes of embedded flash memory for programs and data ?option bytes the option bytes are used to write-protect the memory (with 4 kb granularity) and/or readout-protect the whole memory with the following options: ? level 0: no readout protection ? level 1: memory readout protection, the flash memory cannot be read from or written to if either debug features are connected or boot in ram is selected ? level 2: chip readout protection, debug features (cortex-m0 serial wire) and boot in ram selection disabled 3.3 cyclic redundancy check calculation unit (crc) the crc (cyclic redundancy check) calculation unit is used to get a crc code from a 96-bit data word and a fixed generator polynomial. among other applications, crc-based techniques are used to verify data transmission or storage integrity. in the scope of the en/iec 60335-1 standard, they offer a means of verifying the flash memory integrity. the crc ca lculation unit helps co mpute a signature of the software during runtime, to be compared with a reference signature generated at link- time and stored at a given memory location.
stm32f051x functional overview doc id 018746 rev 2 11/22 3.4 direct memory access controller (dma) the 5-channel general-purpose dmas manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. the dma supports circular buffer management, removing the need for user code intervention when the controller reaches the end of the buffer. each channel is connected to dedicated hardware dma requests, with support for software trigger on each channel. configuration is made by software and transfer sizes between source and destination are independent. dma can be used with the main peripherals: spi, i2s, i2c, usart, all timx timers (except tim14), dac and adc. 3.5 nested vectored interrupt controller (nvic) the stm32f051xx family embeds a nested vectored interrupt controller able to handle up to 32 maskable interrupt channels (not including the 16 interrupt lines of cortex?-m0) and 16 priority levels. closely coupled nvic gives low latency interrupt processing interrupt entry vector table address passed directly to the core closely coupled nvic core interface allows early processing of interrupts processing of late arriving higher priority interrupts support for tail-chaining processor state automatically saved interrupt entry restored on interrupt exit with no instruction overhead this hardware block provides flexible interrupt management features with minimal interrupt latency. 3.6 extended interrupt/ event controller (exti) the external interrupt/event controller consists of 24 edge detector lines used to generate interrupt/event requests and wake-up the system. each line can be independently configured to select the trigge r event (rising edge, falling edge, both) and can be masked independently. a pending register maintains the status of the interrupt requests. the exti can detect an external line with a pulse width shorter than the internal clock period. up to 55 gpios can be connected to the 16 external interrupt lines.
functional overview stm32f051x 12/22 doc id 018746 rev 2 3.7 clocks and startup system clock selection is performed on startup, however the internal rc 8 mhz oscillator is selected as default cpu clock on reset. an ex ternal 4-32 mhz clock can be selected, in which case it is monitored for failure. if failure is detected, the system automatically switches back to the internal rc oscillato r. a software interrupt is genera ted if enabled. similarly, full interrupt management of the pll clock entry is available when necessary (for example on failure of an indirectly used extern al crystal, resonator or oscillator). several prescalers allow the application to configure the frequency of the ahb and the apb domains. the maximum frequency of t he ahb and the apb domains is 48 mhz. 3.8 boot modes at startup, the boot pin and boot selector option bit are used to select one of three boot options: boot from user flash boot from system memory boot from embedded sram the boot loader is located in system memory. it is used to reprogram the flash memory by using usart1. 3.9 power management 3.9.1 power supply schemes v dd = 2.0 to 3.6 v: external power supply for i/os and the internal regulator. provided externally through v dd pins. v dda = 2.0 to 3.6 v: external analog power supply for adc, reset blocks, rcs and pll (minimum voltage to be applied to v dda is 2.4 v when the adc and dac are used). the v dda voltage level must be always greater or equal to the v dd voltage level and must be provided first. v bat = 1.6 to 3.6 v: power supply for rtc, external clock 32 khz oscillator and backup registers (through power switch) when v dd is not present. for more details on how to connect power pins, refer to figure 9: power supply scheme . 3.9.2 power supply supervisors the device has integrated power-on reset (por) and power-down reset (pdr) circuits. they are always active, and ensure proper operation above a threshold of 2 v. the device remains in reset mode when the monitored supply voltage is below a specified threshold, v por/pdr , without the need for an external reset circuit. the por monitors only the v dd supply voltage. during the startup phase it is required that v dda should arrive first and be greater than or equal to v dd . the pdr monitors both the v dd and v dda supply voltages, however the v dda power supply supervisor can be disabled (by programming a dedicated option bit) to reduce the power consumption if the application design ensures that v dda is higher than or equal to v dd .
stm32f051x functional overview doc id 018746 rev 2 13/22 the device features an embedded programmable voltage detector (pvd) that monitors the v dd power supply and compares it to the v pvd threshold. an interrupt can be generated when v dd drops below the v pvd threshold and/or when v dd is higher than the v pvd threshold. the interrupt service routine can then generate a warning message and/or put the mcu into a safe state. the pvd is enabled by software. 3.9.3 voltage regulator the regulator has three operating modes: main (mr), low power (lpr) and power down. mr is used in normal operating mode (run) lpr can be used in stop mode where the power demand is reduced power down is used in standby mode: the regulator output is in high impedance: the kernel circuitry is powered down, inducing ze ro consumption (but the contents of the registers and sram are lost) this regulator is always enabled after reset. it is disabled in standby mode, providing high impedance output. 3.10 low-power modes the stm32f051xx family supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: sleep mode in sleep mode, only the cpu is stopped. all peripherals continue to operate and can wake up the cpu when an interrupt/event occurs. stop mode stop mode achieves very low power consumption while retaining the content of sram and registers. all clocks in the 1.8 v domain are stopped, the pll, the hsi rc and the hse crystal oscillators are disabled. the volt age regulator can also be put either in normal or in low power mode. the device can be woken up from stop mode by any of the exti lines. the exti line source can be one of the 16 external lines, the pvd output, rtc alarm, compx, i2c1, usart1 or the cec. the i2c1, usart1 and the cec can be config ured to enable the hsi rc oscillator for processing incoming data. if this is used, the voltage regulator should not be put in the low-power mode but kept in normal mode. standby mode the standby mode is used to achieve the lowest power consumption. the internal voltage regulator is switched off so that the entire 1.8 v domain is powered off. the pll, the hsi rc and the hse crystal oscillators are also switched off. after entering standby mode, sram and register contents are lost except for registers in the backup domain and standby circuitry. the device exits standby mode when an external reset (nrst pin), a iwdg reset, a rising edge on the wkup pins, or an rtc alarm occurs. note: the rtc, the iwdg, and the corresponding clock sources are not stopped by entering stop or standby mode.
functional overview stm32f051x 14/22 doc id 018746 rev 2 3.11 real-time clock (rtc) and backup registers the rtc and the 5 backup registers are supplied through a switch that takes power either on v dd supply when present or through the v bat pin. the backup registers are five 32-bit registers used to store 20 bytes of user application data when v dd power is not present. they are not reset by a system or power reset, or when the device wakes up from standby mode. the rtc is an independent bcd timer/counter. its main features are the following: calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in bcd (binary-coded decimal) format. automatically correction for 28, 29 (leap year), 30, and 31 day of the month. programmable alarm with wake up from stop and standby mode capability. on-the-fly correction from 1 to 32767 rtc clock pulses. this can be used to synchronize it with a master clock. digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal inaccuracy. 2 anti-tamper detection pins with programmable filter. the mcu can be woken up from stop and standby modes on tamper event detection. timestamp feature which can be used to save the calendar content. this function can triggered by an event on the timestamp pin, or by a tamper event. the mcu can be woken up from stop and standby modes on timestamp event detection. the rtc clock sources can be: a 32.768 khz external crystal a resonator or oscillator the internal low-power rc oscillator (typical frequency of 40 khz) the high-speed external clock divided by 32.
stm32f051x functional overview doc id 018746 rev 2 15/22 3.12 timers and watchdogs the stm32f051xx family devices include up to six general-purpose timers, one basic timer and an advanced control timer. ta bl e 3 compares the features of the advanced-control, general-purpose and basic timers. 3.12.1 advanced-control timer (tim1) the advanced-control timer (tim1) can be seen as a three-phase pwm multiplexed on 6 channels. it has complementary pwm outputs with programmable inserted dead times. it can also be seen as a complete general-purpose timer. the 4 independent channels can be used for: input capture output compare pwm generation (edge or center-aligned modes) one-pulse mode output if configured as a standard 16-bit timer, it has the same features as the timx timer. if configured as the 16-bit pw m generator, it has full modu lation capability (0-100%). the counter can be frozen in debug mode. many features are shared with those of the standard timers which have the same architecture. the advanced control timer can therefore work together with the other timers via the timer link feature for synchronization or event chaining. table 3. timer feature comparison timer type timer counter resolution counter type prescaler factor dma request generation capture/compare channels complementary outputs advanced control tim1 16-bit up, down, up/down any integer between 1 and 65536 ye s 4 ye s general purpose tim2 32-bit up, down, up/down any integer between 1 and 65536 ye s 4 n o tim3 16-bit up, down, up/down any integer between 1 and 65536 ye s 4 n o tim14 16-bit up any integer between 1 and 65536 no 1 no tim15 16-bit up any integer between 1 and 65536 ye s 2 ye s tim16, tim17 16-bit up any integer between 1 and 65536 ye s 1 ye s basic tim6 16-bit up any integer between 1 and 65536 ye s 0 n o
functional overview stm32f051x 16/22 doc id 018746 rev 2 3.12.2 general-purpose timers (tim2..3, tim14..17) there are six synchronizable general-purpose timers embedded in the stm32f051xx devices (see ta bl e 3 for differences). each general-purpose timer can be used to generate pwm outputs, or as simple time base. tim2, tim3 stm32f051xx devices feature two synchronizable 4-channel general-purpose timers. tim2 is based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. tim3 is based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. they feature 4 independent channels each for input capture/output compare, pwm or one-pulse mode output. this gives up to 12 input captures/output compares/pwms on the largest packages. the tim2 and tim3 general-purpose timers can work together or with the tim1 advanced- control timer via the timer link feature for synchronization or event chaining. tim2 and tim3 both have independent dma request generation. these timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors. their counters can be frozen in debug mode. tim14 this timer is based on a 16-bit auto-re load upcounter and a 16-bit prescaler. tim14 features one single channel for input capture/output compare, pwm or one-pulse mode output. its counter can be frozen in debug mode. tim15, tim16 and tim17 these timers are based on a 16-bit auto-r eload upcounter and a 16-bit prescaler. tim15 has two independent channels, whereas tim16 and tim17 feature one single channel for input capture/output compare, pwm or one-pulse mode output. the tim15, tim16 and tim17 timers can work together, and tim15 can also operate with tim1 via the timer link feature for synchronization or event chaining. tim15 can be synchronized with tim16 and tim17. tim15, tim16, and tim17 have a complementary output with dead-time generation and independent dma request generation their counters can be frozen in debug mode. 3.12.3 basic timer tim6 this timer is mainly used for dac trigger genera tion. it can also be used as a generic 16-bit time base.
stm32f051x functional overview doc id 018746 rev 2 17/22 3.12.4 independent window watchdog (iwwdg) the independent window watchdog is based on an 8-bit prescaler and 12-bit downcounter with user-defined refresh window. it is clocked from an independent 40 khz internal rc and as it operates independently from the main clock, it can operate in stop and standby modes. it can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. it is hardware or software configurable through the option bytes. the counter can be frozen in debug mode. 3.12.5 system windo w watchdog (wwdg) the system window watchdog is based on a 7-bit downcounter that can be set as free running. it can be used as a watchdog to reset the device when a problem occurs. it is clocked from the apb clock (pclk). it has an early warning interrupt capability and the counter can be frozen in debug mode. 3.12.6 systick timer this timer is dedicated to real-time operating systems, but could also be used as a standard down counter. it features: a 24-bit down counter autoreload capability maskable system interrupt generation when the counter reaches 0. programmable clock source (hclk or hclk/8) 3.13 inter-integrated circuit interfaces (i 2 c) up to two i 2 c interfaces (i2c1 and i2c2) can operate in multimaster or slave modes. both can support standard mode (up to 100 kbit/s) or fast mode (up to 400 kbit/s) and i2c1 supports also fast mode plus (up to 1 mbit/s) with 20 ma output drive. both support 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (2 addresses, 1 with configurable mask). they also include programmable analog and digital noise filters. table 4. comparison of i2c analog and digital filters analog filter digital filter pulse width of suppressed spikes 50 ns programmable length from 1 to 15 i2c peripheral clocks benefits available in stop mode 1. extra filtering capability vs. standard requirements. 2. stable length drawbacks variations depending on temperature, voltage, process disabled when wakeup from stop mode is enabled
functional overview stm32f051x 18/22 doc id 018746 rev 2 in addition, i2c1 provides hardware support for smbus 2.0 and pmbus 1.1: arp capability, host notify protocol, hardware crc (pec) generation/verification, timeouts verifications and alert protocol management. i2c1 also has a clock domain independent from the cpu clock, allowing the i2c1 to wake up the mcu from stop mode on address match. the i2c interfaces can be served by the dma controller. refer to ta b l e 5 for the differences between i2c1 and i2c2. 3.14 universal synchronous/asynchronous receiver transmitters (usart) the device embeds up to two universal synchronous/asynchronous receiver transmitters (usart1 and usart2), which communicate at speeds of up to 6 mbit/s. they provide hardware management of the cts, rts and rs485 de signals, multiprocessor communication mode, master synchronous communication and single-wire half-duplex communication mode. the usart1 supports also smartcard communication (iso 7816), irda sir endec, lin master/slave capability, auto baud rate feature and has a clock domain independent from the cpu clock, allowing the usart1 to wake up the mcu from stop mode. the usart interfaces can be served by the dma controller.serial peripheral interface (spi). refer to ta b l e 6 for the differences between usart1 and usart2. table 5. stm32f051xx i 2 c implementation i2c features (1) 1. x = supported. i2c1 i2c2 7-bit addressing mode xx 10-bit addressing mode xx standard mode (up to 100 kbit/s) xx fast mode (up to 400 kbit/s) xx fast mode plus with 20ma output drive i/os (up to 1 mbit/s) x independent clock x smbus x wakeup from stop x
stm32f051x functional overview doc id 018746 rev 2 19/22 3.15 serial peripheral interface (spi)/inter-integrated sound interfaces (i 2 s) up to two spis are able to communicate up to 18 mbits/s in slave and master modes in full- duplex and simplex communication modes. the 3-bit prescaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16 bits. one standard i 2 s interface (multiplexed with spi1) supporting four different audio standards can operate as master or slave at simplex communication mode. it can be configured to transfer 16 and 24 or 32 bits with16-bit or 32-bit data resolution and synchronized by a specific signal. audio sampling frequency from 8 khz up to 192 khz can be set by 8-bit programmable linear prescaler. when operating in master mode it can output a clock for an external audio component at 256 times the sampling frequency. refer to ta b l e 7 for the differences between spi1 and spi2. table 6. stm32f051xx usart implementation usart modes/features (1) 1. x = supported. usart1 usart2 hardware flow co ntrol for modem x x continuous communication using dma x x multiprocessor communication x x synchronous mode x x smartcard mode x single-wire half-duplex communication x x irda sir endec block x lin mode x dual clock domain and wakeup from stop mode x receiver timeout interrupt x modbus communication x auto baud rate detection x driver enable x x table 7. stm32f051x spi/i2s implementation spi features (1) 1. x = supported. spi1 spi2 hardware crc calculation x x rx/tx fifo x x nss pulse mode x x i2s mode x ti mode x x
functional overview stm32f051x 20/22 doc id 018746 rev 2 3.16 high-definition multimedia interface (hdmi) - consumer electronics control (cec) the device embeds a hdmi-cec controller that provides hardware support for the consumer electronics control (cec) protocol (supplement 1 to the hdmi standard). this protocol provides high-level control functions between all audiovisual products in an environment. it is specified to operate at low speeds with minimum processing and memory overhead. it has a clock domain independent from the cpu clock, allowing the hdmi_cec controller to wakeup the mcu from stop mode on data reception. 3.17 general-purpose in puts/outputs (gpios) each of the gpio pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. most of the gpio pins are shared with digital or analog alternate functions. the i/o configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the i/os registers. 3.18 touch sensing controller (tsc) the device has an embedded independent hardware controlle r (tsc) for controlling touch sensing acquisitions on the i/os. up to 18 touch sensing electrodes can be controlled by the tsc. the touch sensing i/os are organized in 6 acquisition groups, with up to 4 i/os in each group. table 8. capacitive sensing gpios available on stm32f051x devices group capacitive sensing signal name pin name group capacitive sensing signal name pin name 1 tsc_g1_io1 pa0 4 tsc_g4_io1 pa9 tsc_g1_io2 pa1 tsc_g4_io2 pa10 tsc_g1_io3 pa2 tsc_g4_io3 pa11 tsc_g1_io4 pa3 tsc_g4_io4 pa12 2 tsc_g2_io1 pa4 5 tsc_g5_io1 pb3 tsc_g2_io2 pa5 tsc_g5_io2 pb4 tsc_g2_io3 pa6 tsc_g5_io3 pb6 tsc_g2_io4 pa7 tsc_g5_io4 pb7 3 tsc_g3_io1 pb0 6 tsc_g6_io1 pb11 tsc_g3_io2 pb1 tsc_g6_io2 pb12 tsc_g3_io3 pb2 tsc_g6_io3 pb13 tsc_g3_io4 pc5 tsc_g6_io4 pb14
stm32f051x functional overview doc id 018746 rev 2 21/22 3.19 analog to digital converter (adc) the 12-bit analog to digital converter has up to 16 external and 3 internal (temperature sensor, voltage reference, vbat voltage measurement) channels and performs conversions in single-shot or scan modes. in scan mode, automatic conversion is performed on a selected group of analog inputs. the adc can be served by the dma controller. an analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. an interrupt is generated when the converted voltage is outside the programmed thresholds. 3.19.1 temperature sensor the temperature sensor generates a voltage that varies linearly with temperature. the conversion range is between 2 v < v dda < 3.6 v. the temperature sensor is internally connected to the adc_in16 input channel which is used to convert the sensor output voltage into a digital value. as the offset of the temperature sensor varies from chip to chip due to process variation, the internal temperature sensor is mainly suitable for applications that detect temperature changes instead of absolute temperatures. if an accurate temperature reading is needed, then an external temperature sensor part should be used. 3.19.2 v bat battery voltage monitoring this embedded hardware feature allows the application to measure the v bat battery voltage using the internal adc channel adc_in18. as the v bat voltage may be higher than v dda , and thus outside the adc input range, the v bat pin is internally connected to a bridge divider by 2. as a consequence, the converted digital value is half the v bat voltage. table 9. no. of capacitive sensing channels available on stm32f051xx devices analog i/o group number of capacitive sensing channels stm32f051rx stm32f051cx stm32f051kx g1 3 3 3 g2 3 3 3 g3 3 2 2 g4 3 3 3 g5 3 3 3 g6 3 3 0 number of capacitive sensing channels 18 17 14
functional overview stm32f051x 22/22 doc id 018746 rev 2 3.20 digital-to-analog converter (dac) the 12-bit buffered dac channel can be used to convert digital signals into analog voltage signal outputs. the chosen design structure is composed of integrated resistor strings and an amplifier in non-in verting configuration. this digital interface supports the following features: left or right data alignment in 12-bit mode synchronized update capability dma capability external triggers for conversion five dac trigger inputs are used in the device. the dac is triggered through the timer trigger outputs and the dac interface is generating it?s own dma requests. 3.21 fast low power comparators and reference voltage the device embeds two fast rail-to-rail comparators with programmable reference voltage (internal or external), hysteresis and speed (low speed for low power) and with selectable output polarity. the reference voltage can be one of the following: external i/o dac output pin internal reference voltage or submultiple (1/4, 1/2, 3/4). refer to table 21: embedded internal reference voltage for the value and precision of the internal reference voltage. both comparators can wake up from stop mode, generate interrupts and breaks for the timers and can be also combined into a window comparator. the internal voltage reference is also connected to adc_in17 input channel of the adc. 3.21.1 serial wire debug port (sw-dp) an arm sw-dp interface is provided to allow a serial wire debugging tool to be connected to the mcu.
stm32f051x pinouts and pin description doc id 018746 rev 2 23/30 4 pinouts and pin description figure 3. lqfp64 64-pin package pinout 6"!4 0#/3#?). 0&/3#?). .234 0# 0# 0# 0# 633! 6$$! 0! 0! 0! 6$$ 0" 0" "//4 0" 0" 0" 0" 0" 0$ 0# 0# 0# 0! 0! 0& 0& 0! 0! 0! 0! 0! 0! 0# 0# 0# 0# 0" 0" 0" 0" 0! 0& 0! 0! 0! 0! 0# 0# 0" 0" 0" 0" 0" ,1&0 0# -36 0& 633 6$$ 633 0&/3#?/54 0#/3#?/54
pinouts and pin description stm32f051x 24/30 doc id 018746 rev 2 figure 4. lqfp48 48-pin package pinout figure 5. ufqfpn32 32-pin package pinout ,1&0 0! 0! 0! 0! 0! 0" 0" 0" 0" 0" 633 6$$ 0& 0& 0! 0! 0! 0! 0! 0! 0" 0" 0" 0" 6"!4 .234 633! 6$$! 0! 0! 0! 6$$ 633 0" 0" "//4 0" 0" 0" 0" 0" 0! 0! -36 0# 0#/3#?). 0&/3#?). 0&/3#?/54 0#/3#?/54 0! 6$$ .234 0! 0! 0! 0! 0! 0" 0! 6$$ 0! 0! 0! 0! 0! 0! 0" "//4 0" 0" 0" -36 6$$! 0" 0" 0! 0" 0" 0! 0&/3#?). 0&/3#?/54 0! 633 633!
stm32f051x pinouts and pin description doc id 018746 rev 2 25/30 table 10. legend/abbreviations used in the pinout table name abbreviation definition pin name unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name pin type s supply pin i input only pin i/o input / output pin i/o structure ft 5 v tolerant i/o ftf 5 v tolerant i/o, fm+ capable tta 3.3 v tolerant i/o directly connected to adc tc standard 3.3v i/o b dedicated boot0 pin rst bidirectional reset pin with embedded weak pull-up resistor notes unless otherwise specified by a note, all i/os are set as floating inputs during and after reset pin functions alternate functions functions selected through gpiox_afr registers additional functions functions directly selected/enabled through peripheral registers table 11. pin definitions pin number pin name (function after reset) pin type i/o structure notes pin functions lqfp64 lqfp48 ufqfpn32 alternate functions a dditional functions 1 1 vbat s backup power supply 22 pc13 i/otc (1)(2) rtc_tamp1, rtc_ts, rtc_out, wkup2 33 pc14-osc32_in (pc14) i/o tc (1)(2) osc32_in 44 pc15- osc32_out (pc15) i/o tc (1)(2) osc32_out 552 pf0-osc_in (pf0) i/o ft osc_in 663 pf1-osc_out (pf1) i/o ft osc_out 7 7 4 nrst i/o rst device reset input / internal reset output (active low)
pinouts and pin description stm32f051x 26/30 doc id 018746 rev 2 8 pc0 i/o tta eventout adc_in10 9 pc1 i/o tta eventout adc_in11 10 pc2 i/o tta eventout adc_in12 11 pc3 i/o tta eventout adc_in13 12 8 0 vssa s analog ground 13 9 5 vdda s analog power supply 14 10 6 pa0 i/o tta usart2_cts, tim2_ch1_etr, comp1_out, tsc_g1_io1 adc_in0, comp1_inm6, rtc_tamp2, wkup1 15 11 7 pa1 i/o tta usart2_rts, tim2_ch2, tsc_g1_io2, eventout adc_in1, comp1_inp 16 12 8 pa2 i/o tta usart2_tx, tim2_ch3, tim15_ch1, comp2_out, tsc_g1_io3 adc_in2, comp2_inm6 17 13 9 pa3 i/o tta usart2_rx, tim2_ch4, tim15_ch2, tsc_g1_io4 adc_in3, comp2_inp 18 pf4 i/o ft eventout 19 pf5 i/o ft eventout 20 14 10 pa4 i/o tta spi1_nss/i2s1_ws, usart2_ck, tim14_ch1, tsc_g2_io1 adc_in4, comp1_inm4, comp2_inm4, dac1_out 21 15 11 pa5 i/o tta spi1_sck/i2s1_ck, cec, tim2_ch_etr, tsc_g2_io2 adc_in5, comp1_inm5, comp2_inm5 22 16 12 pa6 i/o tta spi1_miso/i2s1_mck, tim3_ch1, tim1_bkin, tim16_ch1, comp1_out, tsc_g2_io3, eventout adc_in6 23 17 13 pa7 i/o tta spi1_mosi/i2s1_sd, tim3_ch2, tim14_ch1, tim1_ch1n, tim17_ch1, comp2_out, tsc_g2_io4, eventout adc_in7 24 pc4 i/o tta eventout adc_in14 25 pc5 i/o tta tsc_g3_io1 adc_in15 26 18 14 pb0 i/o tta tim3_ch3, tim1_ch2n, tsc_g3_io2, eventout adc_in8 table 11. pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes pin functions lqfp64 lqfp48 ufqfpn32 alternate functions a dditional functions
stm32f051x pinouts and pin description doc id 018746 rev 2 27/30 27 19 15 pb1 i/o tta tim3_ch4, tim14_ch1, tim1_ch3n, tsc_g3_io3 adc_in9 28 20 16 pb2 i/o ft tsc_g3_io4 29 21 pb10 i/o ft i2c2_scl, cec, tim2_ch3, tsc_sync 30 22 pb11 i/o ft i2c2_sda, tim2_ch4, tsc_g6_io1, eventout 31 23 0 vss s digital ground 32 24 17 vdd s digital power supply 33 25 pb12 i/o ft spi2_nss, tim1_bkin, tsc_g6_io2, eventout 34 26 pb13 i/o ft spi2_sck, tim1_ch1n, tsc_g6_io3 35 27 pb14 i/o ft spi2_miso, tim1_ch2n, tim15_ch1, tsc_g6_io4 36 28 pb15 i/o ft spi2_mosi, tim1_ch3n, tim15_ch1n, tim15_ch2 rtc_refin 37 pc6 i/o ft tim3_ch1 38 pc7 i/o ft tim3_ch2 39 pc8 i/o ft tim3_ch3 40 pc9 i/o ft tim3_ch4 41 29 18 pa8 i/o ft usart1_ck, tim1_ch1, eventout, mco 42 30 19 pa9 i/o ft usart1_tx, tim1_ch2, tim15_bkin, tsc_g4_io1 43 31 20 pa10 i/o ft usart1_rx, tim1_ch3, tim17_bkin, tsc_g4_io2 44 32 21 pa11 i/o ft usart1_cts, tim1_ch4, comp1_out, tsc_g4_io3, eventout 45 33 22 pa12 i/o ft usart1_rts, tim1_etr, comp2_out, tsc_g4_io4, eventout 46 34 23 pa 1 3 (swdat) i/o ft (3) ir_out, swdat 47 35 pf6 i/o ft i2c2_scl 48 36 pf7 i/o ft i2c2_sda table 11. pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes pin functions lqfp64 lqfp48 ufqfpn32 alternate functions a dditional functions
pinouts and pin description stm32f051x 28/30 doc id 018746 rev 2 49 37 24 pa 1 4 (swclk) i/o ft (3) usart2_tx, swclk 50 38 25 pa15 i/o ft spi1_nss/i2s1_ws, usart2_rx, tim2_ch_etr, eventout 51 pc10 i/o ft 52 pc11 i/o ft 53 pc12 i/o ft 54 pd2 i/o ft tim3_etr 55 39 26 pb3 i/o ft spi1_sck/i2s1_ck, tim2_ch2, tsc_g5_io1, eventout 56 40 27 pb4 i/o ft spi1_miso/i2s1_mck, tim3_ch1, tsc_g5_io2, eventout 57 41 28 pb5 i/o ft spi1_mosi/i2s1_sd, i2c1_smba, tim16_bkin, tim3_ch2 58 42 29 pb6 i/o ftf i2c1_scl, usart1_tx, tim16_ch1n, tsc_g5_io3 59 43 30 pb7 i/o ftf i2c1_sda, usart1_rx, tim17_ch1n, tsc_g5_io4 60 44 31 boot0 i b boot memory selection 61 45 32 pb8 i/o ftf i2c1_scl, cec, tim16_ch1, tsc_sync 62 46 pb9 i/o ftf i2c1_sda, ir_out, tim17_ch1, eventout 63 47 0 vss s digital ground 64 48 1 vdd s digital power supply 1. pc13, pc14 and pc15 are supplied through the power switch. si nce the switch only sinks a limited amount of current (3 ma), the use of gpio pc13 to pc15 in output mode is limited: - the speed should not exceed 2 mhz with a maximum load of 30 pf - these gpios must not be used as a cu rrent sources (e.g. to drive an led). 2. after the first backup domain power-up, pc13, pc14 and pc15 operate as gpios. their function then depends on the content of the backup registers which is not reset by the main reset. for details on how to manage these gpios, refer to the battery backup domain and bkp register des cription sections in the reference manual. 3. after reset, these pins are configur ed as swdat and swclk alternate functi ons, and the internal pull-up on swdat pin and internal pull-down on swclk pin are activated. table 11. pin definitions (continued) pin number pin name (function after reset) pin type i/o structure notes pin functions lqfp64 lqfp48 ufqfpn32 alternate functions a dditional functions
pinouts and pin description stm32f051x 29/30 doc id 018746 rev 2 table 12. alternate functions selected through gpioa_afr registers for port a pin name af0 af1 af2 af3 af4 af5 af6 af7 pa0 usart2_cts tim2_ch1_ etr tsc_g1_io1 comp1_out pa1 eventout usart2_rts tim2_ch2 tsc_g1_io2 pa2 tim15_ch1 usart2_tx tim2_ch3 tsc_g1_io3 comp2_out pa3 tim15_ch2 usart2_rx tim2_ch4 tsc_g1_io4 pa 4 spi1_nss/ i2s1_ws usart2_ck tsc_g2_io1 tim14_ch1 pa 5 spi1_sck/ i2s1_ck cec tim2_ch1_ etr tsc_g2_io2 pa 6 spi1_miso/ i2s1_mck tim3_ch1 tim1_bkin t sc_g2_io3 tim16_ch1 eventout comp1_out pa 7 spi1_mosi/ i2s1_sd tim3_ch2 tim1_ch1n tsc _g2_io4 tim14_ch1 tim 17_ch1 eventout comp2_out pa8 mco usart1_ck tim1_ch1 eventout pa9 tim15_bkin usart1_tx tim1_ch2 tsc_g4_io1 pa10 tim17_bkin usart1_rx tim1_ch3 tsc_g4_io2 pa11 eventout usart1_cts tim1_ch4 tsc_g4_io3 comp1_out pa12 eventout usart1_rts tim1_etr tsc_g4_io4 comp2_out pa 1 3 s w dat i r _ o u t pa14 swclk usart2_tx pa 1 5 spi1_nss/ i2s1_ws usart2_rx tim2_ch1_ etr eventout
stm32f051x pinouts and pin description doc id 018746 rev 2 30/30 table 13. alternate functions selected through gpiob_afr registers for port b pin name af0 af1 af2 af3 pb0 eventout tim3_ch3 tim1_ch2n tsc_g3_io2 pb1 tim14_ch1 tim3_ch4 tim1_ch3n tsc_g3_io3 pb2 tsc_g3_io4 pb3 spi1_sck/i2s1_ck eventout tim2_ch2 tsc_g5_io1 pb4 spi1_miso/i2s1_mck tim3_ch1 eventout tsc_g5_io2 pb5 spi1_mosi/i2s1_sd tim 3_ch2 tim16_bkin i2c1_smba pb6 usart1_tx i2c1_scl tim16_ch1n tsc_g5_io3 pb7 usart1_rx i2c1_sda tim17_ch1n tsc_g5_io4 pb8 cec i2c1_scl tim16_ch1 tsc_sync pb9 ir_out i2c1_sda tim17_ch1 eventout pb10 cec i2c2_scl tim2_ch3 tsc_sync pb11 eventout i2c2_sda tim2_ch4 tsc_g6_io1 pb12 spi2_nss eventout tim1_bkin tsc_g6_io2 pb13 spi2_sck tim1_c h1n tsc_g6_io3 pb14 spi2_miso tim15_ch1 tim1_ch2n tsc_g6_io4 pb15 spi2_mosi tim15_ch2 tim1_ch3n tim15_ch1n
stm32f051x memory mapping doc id 018746 rev 2 31/33 5 memory mapping figure 6. stm32f051x memory map 2eserved !(" x&&&&&&&& 0eripherals 32!- &lashmemory reserved reserved 3ystemmemory /ption"ytes #ortex - )nternal 0er ip h er al s x% -36 'mbti tztufnnfnpsz ps43". efqfoejohpo #005dpogjhvsbujpo x x% x# x! x x x x x y x x&&&%# x&&&& x&&&&# x&&&&&&& x reserved #/$% "1# "1# reserved x x x x reserved x ")# x reserved x&& x&&
memory mapping stm32f051x 32/33 doc id 018746 rev 2 table 14. stm32f051x peripheral register boundary addresses bus boundary address size peripheral 0x4800 1800 - 0x5fff ffff ~384 mb reserved ahb2 0x4800 1400 - 0x4800 17ff 1kb gpiof 0x4800 1000 - 0x4800 13ff 1kb reserved 0x4800 0c00 - 0x4800 0fff 1kb gpiod 0x4800 0800 - 0x4800 0bff 1kb gpioc 0x4800 0400 - 0x4800 07ff 1kb gpiob 0x4800 0000 - 0x4800 03ff 1kb gpioa 0x4002 4400 - 0x47ff ffff ~128 mb reserved ahb1 0x4002 4000 - 0x4002 43ff 1kb tsc 0x4002 3400 - 0x4002 3fff 3kb reserved 0x4002 3000 - 0x4002 33ff 1kb crc 0x4002 2400 - 0x4002 2fff 3kb reserved 0x4002 2000 - 0x4002 23ff 1kb flash interface 0x4002 1400 - 0x4002 1fff 3kb reserved 0x4002 1000 - 0x4002 13ff 1kb rcc 0x4002 0400 - 0x4002 0fff 3kb reserved 0x4002 0000 - 0x4002 03ff 1kb dma 0x4001 8000 - 0x4001 ffff 32kb reserved apb 0x4001 5c00 - 0x4001 7fff 9kb reserved 0x4001 5800 - 0x4001 5bff 1kb dbgmcu 0x4001 4c00 - 0x4001 57ff 3kb reserved 0x4001 4800 - 0x4001 4bff 1kb tim17 0x4001 4400 - 0x4001 47ff 1kb tim16 0x4001 4000 - 0x4001 43ff 1kb tim15 0x4001 3c00 - 0x4001 3fff 1kb reserved 0x4001 3800 - 0x4001 3bff 1kb usart1 0x4001 3400 - 0x4001 37ff 1kb reserved 0x4001 3000 - 0x4001 33ff 1kb spi1/i2s1 0x4001 2c00 - 0x4001 2fff 1kb tim1 0x4001 2800 - 0x4001 2bff 1kb reserved 0x4001 2400 - 0x4001 27ff 1kb adc 0x4001 0800 - 0x4001 23ff 7kb reserved 0x4001 0400 - 0x4001 07ff 1kb exti 0x4001 0000 - 0x 4001 03ff 1kb syscfg + comp 0x4000 8000 - 0x4000 ffff 32kb reserved
stm32f051x memory mapping doc id 018746 rev 2 33/33 apb 0x4000 7c00 - 0x4000 7fff 1kb reserved 0x4000 7800 - 0x4000 7bff 1kb cec 0x4000 7400 - 0x4000 77ff 1kb dac 0x4000 7000 - 0x4000 73ff 1kb pwr 0x4000 5c00 - 0x4000 6fff 5kb reserved 0x4000 5800 - 0x4000 5bff 1kb i2c2 0x4000 5400 - 0x4000 57ff 1kb i2c1 0x4000 4800 - 0x4000 53ff 3 kb reserved 0x4000 4400 - 0x4000 47ff 1kb usart2 0x4000 3c00 - 0x4000 43ff 2kb reserved 0x4000 3800 - 0x4000 3bff 1kb spi2 0x4000 3400 - 0x4000 37ff 1kb reserved 0x4000 3000 - 0x4000 33ff 1kb iwwdg 0x4000 2c00 - 0x4000 2fff 1kb wwdg 0x4000 2800 - 0x4000 2bff 1kb rtc 0x4000 2400 - 0x4000 27ff 1kb reserved 0x4000 2000 - 0x4000 23ff 1kb tim14 0x4000 1400 - 0x4000 1fff 3kb reserved 0x4000 1000 - 0x4000 13ff 1kb tim6 0x4000 0800 - 0x4000 0fff 2kb reserved 0x4000 0400 - 0x4000 07ff 1kb tim3 0x4000 0000 - 0x4000 03ff 1kb tim2 table 14. stm32f051x peripheral register boundary addresses (continued) bus boundary address size peripheral
package characteristics stm32f051x 34/37 doc id 018746 rev 2 6 package characteristics 6.1 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark.
stm32f051x package characteristics doc id 018746 rev 2 35/37 figure 7. lqfp64 ? 10 x 10 mm 64 pin low-profile quad flat package outline (1) figure 8. recommended footprint (1)(2) 1. drawing is not to scale. 2. dimensions are in millimeters. table 15. lqfp64 ? 10 x 10 mm 64 pin low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a 1.600 0.0630 a1 0.050 0.150 0.0020 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 0.200 0.0035 0.0079 d 11.800 12.000 12.200 0.4646 0.4724 0.4803 d1 9.800 10.000 10.200 0.3858 0.3937 0.4016 d. 7.500 e 11.800 12.000 12.200 0.4646 0.4724 0.4803 e1 9.800 10.00 10.200 0.3858 0.3937 0.4016 e 0.500 0.0197 k 03.57 03.57 l 0.450 0.600 0.75 0.0177 0.0236 0.0295 l1 1.000 0.0394 ccc 0.080 0.0031 n number of pins 64 1. values in inches are converted from mm and rounded to 4 decimal digits. 5w_me l a1 k l1 c a a2 ccc c d d1 d3 e3 e1 e 32 33 48 49 b 64 1 pin 1 identification 16 17 48 32 49 64 17 116 1.2 0.3 33 10.3 12.7 10.3 0.5 7.8 12.7 ai14909
package characteristics stm32f051x 36/37 doc id 018746 rev 2 figure 9. lqfp48 ? 7 x 7mm, 48-pin low-profile quad flat package outline (1) figure 10. recommended footprint (1)(2) 1. drawing is not to scale. 2. dimensions are in millimeters. 5b_me l a1 k l1 c a a2 ccc c d d1 d3 e3 e1 e 24 25 36 37 b 48 1 pin 1 identification 12 13 9.70 5.80 7.30 12 24 0.20 7.30 1 37 36 1.20 5.80 9.70 0.30 25 1.20 0.50 ai14911b 13 48 table 16. lqfp48 ? 7 x 7mm, 48-pin low-profile quad flat package mechanical data symbol millimeters inches (1) min typ max min typ max a 1.600 0.0630 a1 0.050 0.150 0.0020 0.0059 a2 1.350 1.400 1.450 0. 0531 0.0551 0.0571 b 0.170 0.220 0.270 0. 0067 0.0087 0.0106 c 0.090 0.200 0.0035 0.0079 d 8.800 9.000 9.200 0. 3465 0.3543 0.3622 d1 6.800 7.000 7.200 0. 2677 0.2756 0.2835 d3 5.500 0.2165 e 8.800 9.000 9.200 0. 3465 0.3543 0.3622 e1 6.800 7.000 7.200 0. 2677 0.2756 0.2835 e3 5.500 0.2165 e 0.500 0.0197 l 0.450 0.600 0.750 0. 0177 0.0236 0.0295 l1 1.000 0.0394 k 03.57 03.57 ccc 0.080 0.0031 1. values in inches are converted from mm and rounded to 4 decimal digits.
stm32f051x package characteristics doc id 018746 rev 2 37/37 figure 11. ufqfpn32 - 32-lead ultra thin fine pitch quad flat no-lead package outline (5x5) (1)(2)(3) figure 12. ufqfpn32 recommended footprint (1)(4) 1. drawing is not to scale. 2. all leads/pads should also be soldered to the pc b to improve the lead/pad solder joint life. 3. there is an exposed die pad on the unders ide of the ufqfpn package. this pad is used for the device ground and must be connected. it is referred to as pin 0 in table 11: pin definitions . 4. dimensions are in millimeters. s e a ting pl a ne ddd c c a 3 a1 a d e 9 16 17 24 3 2 pin # 1 id r = 0. 3 0 8 e l l d2 1 b e2 a0b 8 _me bottom view table 17. ufqfpn32 - 32-lead ultra thin fine pitch quad flat no-lead package (5 x 5), package mechanical data dim. mm inches (1) min typ max min typ max a 0.5 0.55 0.6 0.0197 0.0217 0.0236 a1 0.00 0.02 0.05 0 0.0008 0.0020 a3 0.152 0.006 b 0.18 0.23 0.28 0.0071 0.0091 0.0110 d 4.90 5.00 5.10 0.1929 0.1969 0.2008 d2 3.50 0.1378 e 4.90 5.00 5.10 0.1929 0.1969 0.2008 e2 3.40 3.50 3.60 0.1339 0.1378 0.1417 e 0.500 0.0197 l 0.30 0.40 0.50 0.0118 0.0157 0.0197 ddd 0.08 0.0031 number of pins n32 1. values in inches are converted from mm and rounded to 4 decimal digits.
ordering information scheme stm32f051x 38/38 doc id 018746 rev 2 7 ordering information scheme for a list of available options (memory, package, and so on) or for further information on any aspect of this device, please contact your nearest st sales office. example : stm32 f 051 r 8 t 6 x device family stm32 = arm-based 32-bit microcontroller product type f = general-purpose sub-family 051 = stm32f051xx pin count k = 32 pins c = 48 pins r = 64 pins code size 4 = 16 kbytes of flash memory 6 = 32 kbytes of flash memory 8 = 64 kbytes of flash memory package u = ufqfn t = lqfp temperature range 6 = ?40 c to +85 c 7 = ?40 c to +105 c options xxx = programmed parts tr = tape and real
stm32f051x revision history doc id 018746 rev 2 39/40 8 revision history table 18. document revision history date revision changes 09-feb-2012 1 initial release 14-feb-2012 2 added table 2: stm32f051xx family device features and peripheral counts updated table 7: stm32f051x spi /i2s implementation
stm32f051x 40/40 doc id 018746 rev 2 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by two authorized st representatives, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2012 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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